The rate of innovation in computer technology and more particularly in desktop computers is phenomenal, as known by users of computers. It is also highly visible that software makers create new products and versions to support the latest advances in processing speeds, memory size and hard disk capacity, while hardware vendors release new devices and technologies to keep up with the demands of the latest software. As data acquisition rates increase with advances in silicon technologies, larger amounts of data must be transferred to the PC for processing. These transfers are handled by the data bus connecting the data to the PC memory. However, the rate at which data transfers occur is often the bottleneck in measurements, and is the primary reason that many instruments have incorporated expensive onboard memory.
To address the growing appetite for bandwidth, a new bus technology called PCI Express (known as the PCIe) has been introduced. Originally designed to enable high speed audio and video streaming, PCIe devices are also being used to improve the data rate from measurement devices to PC memory by up to 30 times versus the traditional PCI bus used on older generation desktops.
Developments in PCIe; PCIe was introduced by industry to overcome the limitations of the original PCI bus. Developed and released by Intel® over a decade ago, the original PCI bus operated at 33 MHz and 32 bits with a peak theoretical bandwidth of 132 MB per second. In the implementation of the PCI bus, the bus bandwidth is shared among multiple devices, to enable communication among the different devices on the bus. As devices evolved, new bandwidth hungry devices began starving other devices on the same shared bus. To provide the bandwidth required by these modern devices, PCIe was developed by an industry consortium of PC and peripheral vendors and began shipping in standard desktop PCs. Already, most desktop machines from the leading suppliers include at least one PCIe slot. As known, the most notable PCIe Express advancement over PCI is its point-to-point bus topology. The shared bus used for PCI is replaced with a shared switch, which provides each device its own direct access to the bus. And unlike PCI which divides bandwidth between all devices on the bus, PCIe provides each device with its won dedicated data pipeline. Data is sent serially in packets through pairs of transmit and receive signals called lanes, which enable 250 MBytes/s bandwidth per direction, per lane. Multiple lanes can be grouped together into ×1 (“by-one”), ×2, ×4, ×8, ×12, ×16, and ×32 lane widths to increase bandwidth to the slot.
PCIe dramatically improves data bandwidth compared to legacy buses, minimizing the need for onboard memory and enabling faster data streaming. Notably, because of the sealable lane topology of PCIe, data acquisition vendors can implement a PCI Express connector with the number of lanes suitable to the requirements of the device.
Software compatibility is also ensured by the PCI Express specification. At boot time, generally the operating system can discover all of the PCIe devices present and then allocate system resources such as memory, I/O space, and interrupts to create an optimal system environments. And because the PCIe physical layer is generally transparent to application software, programs originally written for PCI devices can run unchanged on PCIe devices that have the same functionality, and PCI and PCIe devices can be used together in the same system. This retroactive compatibility of PCIe software with traditional PCI is helpful in preserving the software interests of both vendors and users.
Multifunction PCIe devices according to specification will generate unique types of events targetted to the root complex to indicate error conditions through a link. Those events if not dealt with across different functions, will result in a situation where too many events flood the link, thus reducing link bandwidth. It is noted that the specification for a PCExpress multifunction device limits the multifunction device to generating only a limited number of error messages per event. A method is therefore needed to determine which of the functions will be allowed to issue an error message when an event occurs.